As integrated circuits are produced with greater and greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, high fault coverage of several types of fault models becomes more difficult to achieve with traditional testing paradigms. This difficulty arises for several reasons. First, larger integrated circuits have a very high and still increasing logic-to-pin ratio that creates a test data transfer bottleneck at the chip pins. In addition, larger circuits require a prohibitively large volume of test data that must be then stored in external testing equipment. Moreover, applying the test data to a large circuit requires an increasingly long test application time. Furthermore, present external testing equipment is unable to test such larger circuits at their speed of operation.
Integrated circuits are presently tested using a number of structured design for testability (DFT) techniques. The scan-path method is a widely used DFT technique. It is based on serialization of test data (see E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, Englewood Cliffs, N.J., USA, 1986). In scan-based testing, the flip-flops in the circuit under test are connected together to form one or multiple scan chains. Through these scan chains, arbitrary test patterns can be shifted into the flip-flops and applied to different parts of the circuit. The main advantage of scan testing is improving the controllability and observability of the circuit under test by having direct access to the states of the flip-flops.
In scan-path methods, the circuit is designed so that it has two modes of operation: a normal functional mode and a scan mode. In the scan mode, the flip-flops in the circuit are connected as a shift register so that it is possible to shift an arbitrary test pattern into the flip-flops. The test pattern is applied by returning the circuit to the normal mode for one clock cycle during which the contents of the flip-flops are applied to the combinational circuitry and the outputs of the combinational circuitry are stored back in the flip-flops. The circuit can then be placed in the scan mode to shift out the contents of the flip-flops and compare them with the correct response. Shifting the response out may be implemented concurrently while shifting in a new test pattern.
Scan-based testing of VLSI (Very Large Scale Integration) circuits is widely used due to its simplicity and the fact that it permits more thorough testing of the circuit. However, it suffers from the following four problems: (1) data volume: Every test pattern requires N bits of storage where N=number of primary inputs+number of flip-flops in the design. With hundreds of thousands of flip-flops and tens of thousands of patterns, the data volume is in Gigabits and the problem is only getting worse; (2) test time: Scanning-in a test pattern is a time consuming process. For example, if the length of the longest scan chain is 4,000 flip-flops, every test pattern needs 4,000 clock cycles to be shifted in the scan chains. Scanning the pattern is normally done at slow speed due to circuit limitations. This problem contributes significantly to the test cost since test time is a major component in that cost function; (3) power consumption: In normal operation, a small portion of the circuit is active at the same time. During scan-in and scan-out, all flip-flops are toggled to shift the pattern in and the response out. This high activity may damage the circuit. One way to deal with it is to apply the scanning at a low speed which makes test time worse; and (4) tester channels: The cost of testers is directly dependent on the number of channels it supports. A solution that would enable testing a circuit with a lower requirement on the number of tester channels should result in reduction in test cost.
Shifting a test pattern into the scan chains is a time consuming process. If the circuit has a single scan chain, shifting a test pattern takes as many clock cycles as there are flip-flops in the circuit. The stumps architecture, shown in FIG. 1, groups the flip-flops into multiple scan chains to enable loading a test pattern into the scan chains in parallel. However, it requires a tester channel per scan chain input to load the test pattern and a tester channel per scan chain output to shift out the circuit response.
Several compression techniques have been presented to reduce the data volume and the tester channel requirements. A generic architecture for such techniques is shown in FIG. 2. With such techniques, a compressed vector is loaded from the tester into the decompression circuitry, which expands the vector into a test pattern in the scan chains. The test response is also compressed into a smaller vector using the output compression circuitry. For example, compression techniques were discussed in B. Koenemann “LFSRCoded Test Patterns for Scan Designs,” European Test Conference (ETC'91), pp. 237-242, 1991; E. J. McCluskey, D. Burek, B. Koenemann, S. Mitra, J. Patel, J. Rajski and J. Waicukauski, “Test Data Compression,” Design & Test of Computers, Vol. 20, No. 2, pp. 76-87, March-April 2003; A. Al-Yamani and E. J. McCluskey, “Seed Encoding for LFSRs and Cellular Automata,” 40th Design Automation Conference (DAC'03), June 2003; and J. Rajski, J. Tyszer, M. Kassab and N. Mukherjee, “Embedded Deterministic Test,” IEEE Transactions on Computer-Aided Design (TCAD), Vol. 23, No. 5, pp. 776-792, May 2004. These techniques reduce the test data volume by applying linear compression techniques to the test data. These techniques rely on having a decompression circuit on the chip to decompress the data coming from the tester. This may also reduce the tester channel requirements because the test data is loaded into the decompression circuitry. However, such compression schemes offer a limited improvement to test time and fail to address power consumption.
Scan segmentation approaches rely on segmenting the scan chains into multiple segments. If the segments have compatible data they are loaded in parallel. If not, the data is loaded serially. Depending on chances of compatibility, these approaches may reduce test data volume, test time and tester channel requirements. However, for segmentation schemes, chances of compatibility become smaller as the number of segments increases. Thus, such schemes do not allow for taking advantage of an aggressive segmentation that would lead to shorter test time. Also, such schemes fail to address power consumption. For example, Illinois Scan Architecture (ISA) was introduced in I. Hamzaoglu and J. Patel, “Reducing Test Application Time for Full Scan Embedded Cores” IEEE International Symposium on Fault Tolerant Computing (FTC'99), pp. 260-267, 1999 to reduce data volume and test application time by splitting the scan chain into multiple segments to reduce test data volume and test application time. The basic architecture for Illinois scan is shown in FIG. 3. A given scan chain is split into multiple segments. Since a majority of the bits in ATPG (Automatic Test Pattern Generation) patterns are don't-care bits, there are chances that these segments may have compatible vectors (i.e., not having opposite care-bits in one location). In this case, all segments of a given chain are configured in a broadcast mode to read the same vector. This speeds up the test vector loading time and reduces the data volume by a factor equivalent to the number of segments. When the segments within a given scan chain are incompatible, the test vector needs to be loaded serially by reconfiguring the segments into a single long scan chain. The fact that a majority of the ATPG bits (95-99%, see T. Hiraide, K.O. Boateng, H. Konishi, K. Itaya, M. Emori and H. Yamanaka, “BIST-Aided Scan Test—A New Method for Test Cost Reduction,” VLSI Test Symposium (VTS'03), pp. 359-364, April 2003) are don't-care bits makes ISA an attractive solution for data volume and test time.
Several enhancements to the scan architecture have been proposed and discussed for multiple reasons. Lee et al. presented a broadcasting scheme where ATPG patterns are broadcasted to multiple scan chains with a core or across multiple cores, and the broadcast mode is used when the vectors going into multiple chains are compatible (see K-J. Lee, J-J. Chen and C-H. Huang, “Broadcasting Test Patterns to Multiple Circuits,” IEEE Transactions on Computer-Aided Design (TCAD), Vol. 18, No. 12, pp. 1793-1802, December 1999). A token scan architecture was introduced to gate the clock to different scan segments while taking advantage of the regularity and periodicity of scan chains (see T-C. Huang and K-J. Lee, “A Token Scan Architecture for Low Power Testing,” International Test Conference (ITC'01), pp. 660-669, October 2001). Another scheme for selective triggering of scan segments was proposed in S. Sharifi, M. Hosseinabadi, P. Riahi and Z. Navabi, “Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture,” International Symposium on Defect and Fault Tolerance (DFT'03), 2003.
A novel scheme was presented in O. Sinanoglu and A. Orailoglu, “A Novel Scan Architecture for Power-Efficient, Rapid Test,” International Conference on Computer-Aided Design (ICCAD'02), pp. 299-303, November 2002 to reduce test power consumption by freezing scan segments that do not have care-bits in the next test stimulus. By only loading the segments that have care-bits, data volume, application time, and test power consumption are all reduced at once. Only one segment of the scan chain is controlled and observed at a time.
A reconfigurable scheme was introduced in S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur and T. Williams, “A Reconfigurable Shared Scan-in Architecture,” VLSI Test Symposium (VTS'03), April 2003 to use mapping logic to control the connection of multiple scan chains. This increases the chances of compatibility between multiple chains and hence makes room for additional compaction.
A new scan architecture was proposed in D. Xiang, J. Sun, M. Chen and S. Gu, “Cost-Effective Scan Architecture and a Test Application Scheme for Scan Testing with Non-scan Test Power and Test Application Cost,” U.S. Patent Application Publication No. 20040153978, filed Dec. 19, 2003, published Aug. 5, 2004 to order the scan cells and connect them based on their functional interaction.
A circular scan scheme was presented in A. Arslan and A. Orailoglu, “CircularScan: A Scan Architecture for Test Cost Reduction,” Design, Automation and Test in Europe Conference and Exhibition (DATE'04), Vol. 2, pp. 1290-1295, Feb. 2004 to reduce test data volume. The basic concept is to use a decoder to address different scan chains at different time. This increases the number of possible scan chains (2N−1 for an N-input decoder). Also, the output of each scan chains is reconnected to its input. This enables reusing the contents of the response captured in the chain as a new test stimulus if they are compatible.
These previous schemes are either limited in how much they can benefit from compatibility between some of the segments or fail to address the issue of power consumption during scan or both.
Another attempt for using decoder-based segmentation is available in P. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Scan Architecture With Mutually Exclusive Scan Segment Activation for Shift- and Capture-Power Reduction,” IEEE Transactions on Computer-Aided Design (TCAD), Vol. 23, No. 7, pp. 1142-1153, July 2004. In this scheme the clocks to various segments are controlled through a regular decoder. The main advantage of the scheme is power reduction during scan and capture. However, the solution does not address data volume, or test application time.
Recently, a scan chain segmentation technique was presented in L. Lay, J. Patel, T. Rinderknecht, and W-T. Cheng, “Logic BIST with Scan Chain Segmentation,” International Test Conference (ITC'04), pp. 57-66, November 2004. The technique is a BIST solution that selectively inserts inversions at some locations in the scan path based on the ATPG patterns to minimize the number of weights required for weighted random patterns to achieve the desired coverage.
The technique in B. Arslan and A. Orailoglu, “Test Cost Reduction Through a Reconfigurable Scan Architecture,” International Test Conference (ITC'04), pp. 945-952, November 2004 is a recent attempt for test cost reduction through scan reconfiguration. The technique is based on finding the matches between the test response of pattern n and the bits of pattern n+1. However, this technique may require very high routing overhead due to the individual addressing of flip-flops just like random access scan presented in H. Ando, “Testing VLSI with Random Access Scan,” IEEE Computer Society Conference (COMPCON'80), pp. 50-52, Feb., 1980 and enhanced in D. H. Baik, K. K. Saluja, and S. Kajihara, “Random Access Scan: A solution to test power, test data volume, and test time,” International Conference on VLSI Design (VLSID'04), pp. 883-888, Jan. 2004. They also felt that the matching could be done with a pseudorandom sequence generated from an LFSR and the match will be equally probable.
In general, these previous techniques that would address one of the foregoing described four problems associated with scan-based testing of VLSI circuits would normally make another problem worse or in the best case not address it. Moreover, the solutions that allow multiple configurations for compatibility do so using mapping logic hardware. However, this hardware may get larger as higher flexibility is needed. Also, changing the design at a late stage (engineering change orders ECOs) may require changing the mapping logic hardware, which causes delay in time to market. In addition, most of the existing solutions for the four foregoing described problems rely on information provided by automatic test pattern generation tools (ATPG tools) about the unspecified bits. However, some ATPG vendors do not provide such information and consider it confidential. Currently there is no solution in the industry that deals with these problems without requiring these unspecified bits information.
Thus, it would be desirable to provide a new test data compression technique which may achieve high compression ratios without requiring any information from the ATPG tool about the unspecified bits.